In recent years, the amounts of information processing required for digital electronic equipment are on the rise. In order to process the large amounts of information, the transfer rate of digital signals in the electronic equipment is also increasing.
In addition, with reduced sizes of substrates and reduced profiles, the quality of the signal transmission deteriorates.
For example, increases in the densities of wires in printed circuit boards make it difficult to ensure sufficient spacing of the wires. At portions where the spacing of the wires is small, the quality of the signal transmission is deteriorated by noise.
In order to address such deterioration of the quality of the signal transmission, there is a known technology for estimating a portion where the quality of the signal transmission deteriorates. In the technology, a load (a wire parasitic load) that is parasitic in a wire model is calculated at a design stage and a portion where the wire parasitic load varies is detected.
Japanese Laid-open Patent Publication Nos. 9-44550, 5-54092, and 2002-163320 are examples of related art.
When diverse types (e.g., differential wire and single wire) of wire model to be determined and diverse types (e.g., clock and data) of signal are available, it is difficult to determine, in each wire model, sections in which characteristic impedances are to be calculated.
When three-dimensional electromagnetic analyzing software or the like is used to calculate the characteristic impedance of the wire model, there is a problem of requiring a large amount of time for computation processing.